Coherent memory controllers enforce rules on request completion order between masters to allow multiple of these masters to operate on the same data set or within a cache block data set. Maintain coherence required endpoint memory updates to commit in the same order enforced by the coherence controller. Typically the endpoint memory controller sits downstream (after) the coherence controller and implements reordering performance optimizations.
The endpoint memory has a standard master/slave interface with the memory controller and requires all of the proper signals driven to track outstanding accesses. These signals include transaction IDs. Master initiated read and write commands typically are assigned their own IDs. The memory controller must initiate snoop operations to maintain coherence. Sometimes the responses for these include updated data that must be committed to the endpoint memory. This queue also tracks the outstanding IDs given to these memory controller initiated coherence operations and ensures full utilization of all IDs without unnecessary stalling.
A multi-core shared memory controller will typically be employed with memory types that re-order memory accesses to collect accesses to the same page together. Many memories provide faster response when accessing the same page sequentially rather than changing pages. This re-ordering is a problem for a coherent memory system which requires strict ordering to preserve coherence. This invention tracks address hazards to preserve coherence.